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AppliedMicro unveils 100Gbps CMOS multiplexer chip

16 August 2012

 

AppliedMicro has announced the first CMOS merchant multiplexer chip for 100Gbps coherent optical transmission. The S28032 device supports dual polarisation, quadrature phase-shift keying (DP-QPSK) and has a power consumption of 4W, half that of current multiplexer chip designs implemented in BiCMOS. 

 

 

The availability of a CMOS merchant device is welcome news for optical transport suppliers and 100Gbps coherent module makers. CMOS has better economics than BiCMOS due to the larger silicon wafers used and the chip yields achieved. 
 
The device’s reduced power consumption also aids the move to smaller-sized optical modules than the current 5x7-inch MSA. "By reducing the power and the size, we can get to a 4x6-inch next-generation module,” says Tim Warland, product marketing manager, connectivity solutions at AppliedMicro. “And perhaps if we go for a shorter [optical transmission] reach - 400-600km - we could get into a CFP; then you can get four modules on a card.”
 
The S28032 has a CAUI interface: 10x12Gbps input lanes that are multiplexed into four lanes at 28Gbps to 32Gbps. The particular data rate depends on the forward error correction (FEC) scheme used. 
 
The device also supports the SFI-S interface - 21 input channels, each at 6Gbps. This is significant as it enables the S28032 to be interfaced to NTT Electronics' (NEL) DSP-ASIC coherent receiver chip that has been adopted by 100Gbps module makers such as Oclaro and Opnext (now merged) and system vendors including Fujitsu Optical Systems and NEC.
 
The SFI-S interface can also be used to interface to FPGAs, for those system vendors that have their own custom FPGA-based FEC designs.
 
AppliedMicro is sampling the device to lead customers and will start volume production in the 1Q of 2013.
 
By Roy Rubenstein