Next show in
 d  h  m
Back

Inphi first with chips to enable high-density 100G ports

28 September 2011
 
Fabless semiconductor firm Inphi has announced the industry’s first 100Gbps physical layer (PHY) chip manufactured using standard CMOS processes. Also known as a “gearbox” IC, the PHY is a key component inside pluggable 100Gbps modules in the CFP form factor. It converts 10 electrical lanes at 10Gbps into 4 lanes at 25Gbps.
First generation parts tend to get built in silicon-germanium for performance reasons, but they are power hungry, area intensive and expensive, says Siddarth Sheth, vice-president of marketing for Inphi. The IN112510 is a single-chip PHY that consumes just 2.5W.  It replaces current products that require two chips, consume 8W and cost more than $2,000, he claims.
 
In addition, by using standard CMOS manufacturing, Inphi can take advantage of the economies of scale in the digital electronics industry, to deliver higher volumes at lower costs. “The gearbox PHY should help reduce the price of CFP modules and thereby reduce the primary barrier for greater 100GbE deployment,” said Jag Bolaria, senior analyst with the Linley Group.
 
Inphi’s new chip is also ready to support next-generation CFP modules, where the PHY is brought out of the module and onto the line card, enabling eight and eventually 16 ports per line card.
 
Inphi also announced two complementary devices for building 100Gbps modules:  the IN012525 clock-data recovery (CDR) chip and IN2841TA transimpedance amplifier/limiting amplifier (TIA/LIA).
 
Samples of all products are available now, with production shipments starting in 2012.
 
By Pauline Rigby