Next show in
 d  h  m
11 August 2011
ClariPhy Communications will start volume production of its 40 Gbps coherent IC by the end of September.  The fabless semiconductor company raised $14 million in June, part of which will fund the move to production.
The 40Gbps coherent chip, the CL4010, is implemented using a 40nm CMOS process. The device integrates analogue-to-digital and digital-to-analogue converters, a digital signal processor and a multiplexer/demultiplexer on-chip. “Normally the mux is a separate chip and we have integrated that,” said Reza Norouzian, ClariPhy’s vice-president of worldwide sales and business development. 
ClariPhy provides ASIC design services as well as the CL4010, giving customers access to its silicon intellectual property portfolio.
Norouzian expects the 40Gbps market to continue to grow for at least the next three years, before 100Gbps designs mature. The company says several system vendors and module makers have adopted its CL4010.  The CL4010 has also been shown to interoperate with Cortina Systems’ optical transport network (OTN) processor family of devices, says the company.
ClariPhy is also busy developing its 100Gbps coherent ASIC, the CL10010. Using the latest CMOS process will enable 100 million gates on a chip, allowing the integration of soft-decision forward error correction (SD-FEC) while reducing the chip’s power dissipation.  The company acknowledges it will not be first to market with a 100Gbps ASIC, but by using 28nm CMOS process technology it will be well positioned once volume 100Gbps deployments start from 2014.
The biggest investor in the latest funding round was Nokia Siemens Networks (NSN).  An NSN spokesperson said working with ClariPhy will help the system vendor develop technology beyond 100Gbps. “It also gives us a clear competitive edge in the optical network markets, because ClariPhy’s coherent IC and technology portfolio will enable us to offer differentiated and scalable products,” said the spokesperson.
Moving from 100Gbps to 200Gbps wavelengths will require higher order modulation, says Norouzian, and this is well within the capabilities of ClariPhy’s current ASIC designs.  Going to 400Gbps will require two devices used in parallel.
Achieving one Terabit transmission, however, will be far harder. “Going to one Terabit requires a whole new decade of development,” said Norouzian.
By Roy Rubenstein