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EZchip details the industry

19 July 2011
The first disclosed 200Gbps data plane network processor has been announced by fabless chip company EZchip Semiconductor. The NP-5 has double the packet processing performance compared to the company’s existing NP-4 network processor and will sample from year-end 2012.


The NP-5 is being aimed at router and transport switch platforms that comprise the carrier Ethernet switch router (CESR) market. Infonetics Research forecasts that the CESR market will double between 2010 and 2015 to reach US $20bn.
The NP-5’s main functions include programmable packet processing and traffic management. Other functional on-chip blocks include an integrated Ethernet switch fabric adaptor, media access controllers (MACs) that support 1, 10, 40 and 100 Gigabit Ethernet (GbE), and a redesigned memory controller that allows the use of DDR3-only memory to reduce system cost.
Bob Wheeler, senior analyst at The Linley Group says the NP-5 is noteworthy mainly because it reduces a full-duplex 100Gbps packet processor and traffic manager to one chip. Integration is important as line cards move from 100Gbps to 400Gbps in density, he says.
The device will be capable of processing 300 million packets-per-second, each 64 bytes long. And using 24 integrated 10Gbps ports on-chip, the NP-5 can support peak flows of 240Gbps, corresponding to a 2.4:1 oversubscription rate.
The NP-5 also has four integrated engines. Each engine supports either 12 x 10GbE, 3 x 40GbE, 1 x 100GbE or one Interlaken interface. Two of the four interface engines support 48 x 1GbE ports using the QSGMII interface while the remaining two support 12 x 1GbE ports using the SFI interface. The QSGMII interface allows a quadrupling of the links by interleaving four ports per link. The SFI interface allows a direct connection to a 1GbE optical module.
The NP-5 will be implemented using 28nm CMOS and consume 50W.  With samples available from the end of 2012 and assuming an 18-month design cycle, it will be mid-2014 before NP-5 line cards supporting multiple 100Gbps interfaces are deployed.
By Roy Rubenstein