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PMC-Sierra

15 June 2011
 
A new system-on-chip (SOC) from PMC-Sierra could give 40Gbps systems a new lease of life.  Dubbed POLO 40, the new chip is a highly integrated off-the-shelf solution that provides coherent detection capability for metro, regional and long-haul 40Gbps transmission equipment.
 
An integrated solution has multiple benefits: equipment makers will be able to double faceplate density, reduce power consumption by more than 50% compared to non-coherent 40Gbps implementations, and hence drive down the cost per bit transmitted.
 
Several optical suppliers already offer coherent 40Gbps solutions, with Nortel (since bought by Ciena) being the first to market.  However, these solutions usually occupy two or even three line-card slots to house separate analogue-to-digital converter (ADC) chips and digital signal processors (DSPs) plus all the associated optical components and driver ICs.  PMC-Sierra’s chip integrates the DSP engine with transmitter and receiver modulation coding, OTN framing and forward error correction (FEC) capability. The result is “an unmatched level of integration”, the company claims.
 
“The 40G coherent devices provide choices for OEMs, which previously had few options other than to develop ASICs [application specific integrated circuits],” explained Jag Bolaria, senior analyst at the Linley Group, in his firm’s newsletter. “The availability of these devices should reduce implementation costs and increase the deployment of coherent networking.”
 
The POLO 40 also offers – in addition to industry standard G.709 FEC – a proprietary FEC scheme, christened “swizzle”, which is said to improve optical performance by more than 2dB giving a 25% extension to the transmission distance.
 
The POLO 40G is a 43—50Gbps transceiver SOC offering coherent modulation and intradyne detection support for dual-polarisation quadrature phase-shift keying (DP-QPSK).  The chip supports interface and power requirements for common optical module form factors, including 300-pin MSA and next-generation CFP2 modules.
 
PMC-Sierra’s chip is expected to sample in Q3, and be in production in early 2012.  The device is implemented in 40nm CMOS technology and packaged in a 480-pin 23mm x 23mm FCBGA package.
 
By Pauline Rigby