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Avago claims industry first with 30Gbps SerDes

14 February 2011.

Avago Technologies has demonstrated its first serial/deserialiser (SerDes) implemented in a 28nm CMOS process technology. The company admits that other firms have adopted 28nm CMOS but Avago claims its SerDes, for embedded application-specific integrated circuits (ASICs) designs, is the first to be demonstrated operating at 30 Gbps.
 
The SerDes Intellectual Property (IP) design is suited for several high-speed interfaces including CEI-28 and the emerging high-speed Fibre Channel standard, 32GFC.  The CEI-28G is the electrical specification for 28 Gbaud-per-second signalling which is used across four channels to implement 100 Gigabit interfaces. In particular, CEI-28G is used for chip-to-chip and chip-to-module applications for 100 Gigabit Ethernet and 100 Gigabit Optical Transport Network (OTN).
 
The 32 Gigabit Fibre Channel standard - 32GFC - will likely use a 28.5Gbps channel and is another market suited to the 28nm-process SerDes.
 
Avago says it will also use the latest CMOS technology for such interfaces as PCI Express, the IEEE 802.3ba (40 and 100 Gigabit Ethernet), IEEE 802.3az (Energy Efficient Ethernet), Gigabit Ethernet, and such standards as 10GBASE-KR, KX, KX4, KR4, XFI and SFI. The latest process will also be used for custom interfaces specified by Avago’s customers.
 
Having demonstrated the design, Avago says it will evaluate the 28nm process silicon in the second half of 2011, coinciding with its customers’ product plans.
 
The company has also announced it has shipped over 150 million SerDes cores. Avago began shipping embedded SerDes in 2000, starting at 1.25Gbps. The largest percentage of the 150m Serdes have been used in proprietary high-speed interfaces.  As for the rest, the bulk has been for Fibre Channel, the XAUI interface, Ethernet up to 10 Gigabit and 10GBASE-KR used for backplanes.
 
By Roy Rubenstein.